The present invention relates to a semiconductor device and a technique for manufacturing such device, and, more particularly, to a technique that is effectively applied to a semiconductor device having a DRAM (Dynamic Random Access Memory).
A plurality of word lines and a plurality of bit lines are arranged in a matrix shape on a main surface of a semiconductor substrate. Memory cells of a DRAM are located at respective intersections where both lines meet. Each of the memory cells comprises a memory cell selection MISFET (Metal Insulator Semiconductor Field Effect Transistor) and an information storage capacity element (capacitor) connected thereto in a series. The memory cell selection MISFET is formed in an active region surrounded by an element isolation region. The memory cell selection MISFET mainly comprises a gate oxide film, a gate electrode integrally formed with a word line, and a pair of semiconductor regions having a source and a drain. The bit lines are arranged above the memory cell selection MISFETs, respectively, and electrically connected to one of the source and the drain that are shared with two adjacent memory cell selection MISFETs in a direction extended along the bit lines. The information storage capacity element is also located above the memory cell selection MISFET and electrically connected to the other of the source and the drain.
Japanese Patent Application Laid-open No. 7-7084 discloses a DRAM having a Capacitor Over Bitline structure where an information storage capacity element is arranged above a bit line. In such disclosed DRAM, in order to compensate for a decreasing amount of storage electric charge (Cs) of the information storage capacity element due to fineness of the memory cell, an surface area thereof is increased by forming, in a cylindrical shape, a lower electrode (a storage electrode) of the information storage capacity element located above the bit line, and a capacity insulation film and an upper electrode (a plate electrode) are formed thereabove. As the capacity insulation film, a stack insulation film formed by both silicon oxide film and silicon nitride film is used.
However, as the DRAM develops in both high integration and fineness, the surface area of the lower electrode is reduced. Therefore, the capacity insulation film comprising the stack insulation film formed by both silicon oxide and silicon nitride films, has difficulty securing enough amount of storage electric charge. Meanwhile, if film thickness of the capacity insulation film is reduced to secure enough amount of storage electric charge, leak current between the upper electrode and the lower electrode is increased so that refresh characteristics (reliability) of the DRAM is increased. Accordingly, means are needed in which a necessary amount of the storage electric charge is secured even in a capacity insulation film having enough film thickness to restrict generation of the leak current, and various methods for performing the means are proposed.
One of the methods is a method for using the capacity insulation film made of a highly dielectric or ferroelectric material, thinning the film thickness of the capacity insulation film effective in case where the capacity insulation film is converted into the silicon oxide film, and securing enough capacity value. A tantalum oxide film is typically used as such an insulating film. Technologies for using the tantalum oxide film as a capacity insulating film are described in pages 853-855 and 862-864 of xe2x80x9cExtended Abstracts of the 1993 International Conference on Solid State Device and Materials, Makuharixe2x80x9d, or in page 728 of xe2x80x9cAbstracts of the 43rd Associated Exhibition for Applied Physicsxe2x80x9d, or the like.
Further, since tantalum oxide film is generally formed by means of CVD method using organic tantalum gas, it is difficult to form the tantalum oxide film by deposition at high temperature. Therefore, the tantalum oxide film being in an as-deposited state is in an amorphous state, so that it is necessary to crystallize it after being treated thermally in order to obtain a capacity insulation film having a high permittivity. On the other hand, methods have been proposed which reform the tantalum oxide film by heat or plasma treatment under an oxidizing atmosphere of about 400xc2x0 C. for avoiding heat treatment under high temperature.
However, the tantalum oxide film reformed by heat or plasma treatment is not crystallized and remains in an amorphous state. If being used as a capacity insulating film, the amorphous tantalum oxide film can not have a high permittivity. And, non-crystallized tantalum oxide film is degraded in film quality by heat treatment (performed, for example, at between 400 and 600xc2x0 C.) or the like for obtaining electrical conduction of connecting portions between distributing wires provided after an information storage capacity element is formed and another distributing wires or substrate provided below the distributing wires. Therefore there is the drawback that reliability of the DRAM is decreased because of, for example, increase of leak current generated in the capacity insulation film or the like.
On the other hand, the tantalum oxide film being in an amorphous state requires heat treatment at more than 750xc2x0 C. for crystallization thereof if an underlying layer thereof is made of silicon, oxide or nitride of the silicon, or the like. While the crystallized tantalum oxide film does not give rise to any degradation in film quality if being subjected to heat treatment thereafter, the following problems arise when the DRAM has a COB structure.
In the DRAM having the COB structure, before an information storage capacity element is formed, bit lines are provided together with first distributing wires layer in a peripheral circuit formed on the same layer that the bit lines are arranged on. A connecting part between the first distributing wires layer in this peripheral circuit region and the semiconductor substrate is normally provided with a metal silicide film in order to reduce a connecting resistance. If the DRAM having such structure is heat-treated at more than 750xc2x0 C. as described above, the metal silicide film of said connecting part is affected by the heat treatment to raise the connecting resistance. Thereby, in the worst case, there is a problem of destruction of the metal silicide film.
Additionally, whether being crystallized or not, the tantalum oxide film has to be treated in an oxidizing atmosphere. Oxidization of the underlying substrate under such oxidation treatment causes the following problems. That is, if lower electrodes which are underlying are made of silicon, silicon oxide film is formed between the lower electrodes and the tantalum oxide film, film thickness of capacity insulation film is effectively increased because of insulator films having lower permittivity in the tantalum oxide film. Thereby, the capacity insulation element can not have enough capacitance value to be desired. On the other hand, if the lower electrodes which are underlying are made of metal such as titanium nitride, tungsten or the like, a case where the oxide is an insulator film causes increase of the capacity insulator film in film thickness as described above, too. Or, a case where the oxide is formed by electric conductor materials causes cubic expansion due to formation of the metal oxide, and increases leak current in the tantalum oxide film because of stress influencing the tantalum oxide film.
An object of the present invention is to provide a capacity insulation film that has both high heat resistance and reliability and that can increase an amount of storage electric charge thereof.
And, an object of the present invention is to provide a technique for crystallizing the tantalum oxide film by heat treatment at low temperature, without degrading the metal silicide film of the connecting part for distributing wires.
And, an object of the present invention is to provide a technique for suppressing oxidation of the underlying substrate when the tantalum oxide film is crystallized.
And, an object of the present invention is to provide a technique for processing a DRAM that suppresses increase of the connecting resistance to the connecting part in the peripheral circuit region, and that has a capacity insulation element therein with high permittivity, thereby being capable of obtaining high integration, performance and reliability.
Above-mentioned and other objects and novel features of the present invention will become clear through the following description which is made by referring to the accompanying drawings.
Among embodiments of invention disclosed by the present application, summaries of several representative embodiments will briefly described below.
(1) A semiconductor device of the present invention comprises: a substrate of a semiconductor or a substrate having a semiconductor layer as a surface thereof; a memory cell selection MISFET formed on a main surface of the substrate; and an information storage capacity element having a first electrode, a second electrode and a capacity insulating film, the first electrode being electrically connected to a semiconductor region functioning as source or drain of the memory cell selection MISFET, the second electrode being formed opposite to the first electrode, the capacity insulating film being put between the first and second electrodes wherein the first electrode includes a metal or a crystal film of an oxide thereof or a crystal film of nitride thereof which are oriented in a particular plane bearing.
With such a semiconductor device, since the first electrode has a crystal film of metal or oxide of nitride thereof oriented in a particular plane bearing on the surface, an amorphous film containing crystal in an as-deposited state is formed in the capacity insulating film that is formed on the crystal film. Then, temperature of the heat treatment can be lowered to suppress the possible thermal degradation of the members that are prepared in advance.
(2) And, a semiconductor device of the present invention comprises: a substrate of a semiconductor or a substrate having a semiconductor layer as a surface thereof; a memory cell selection MISFET formed on a main surface of the substrate; and an information storage capacity element having a first electrode, a second electrode and a capacity insulating film, the first electrode being electrically connected to a semiconductor region functioning as source or drain of the memory cell selection MISFET, the second electrode being formed opposite to the first electrode, the capacity insulating film being put between the first and second electrodes wherein the first electrode includes a metal oxide film having an rugged surface.
With such a semiconductor device, since the surface of the first electrode has an enlarged area, the accumulated electric charge of the information storage capacity element can be increased.
A metal film containing a crystal oriented in a particular plane bearing may be formed on a surface of the metal oxide film of the first electrode. Then, as in the case of (1) above, temperature of the heat treatment can be lowered to suppress the possible thermal degradation of the members that are prepared in advance.
In the semiconductor device according to (1) or (2) above, the metal element contained in the first electrode may be ruthenium (Ru), tungsten (W), iridium (Ir) or platinum (Pt).
The capacity insulating film may be a metal oxide film having a crystal structure. A typical example of the metal oxide film is a polycrystalline tantalum oxide film.
The crystal of the metal oxide film or the tantalum oxide film may be oriented in a plane bearing same as the crystal contained in the first electrode. Both the crystal contained in the first electrode and the crystal contained in the capacity insulating film may have a crystal structure of hexagonal system and be oriented in a (002) plane.
In the semiconductor device according to (1) or (2) above, the second electrode may be made of metal or metal oxide. Examples of materials that can be used for the second electrode include a tantalum nitride (TiN) film, a ruthenium oxide (RuO) film, a ruthenium (Ru) film and a tungsten (W) film.
In the semiconductor device according to (1) or (2) above, a film of oxide of the metal element contained in the first electrode may be formed on the interface of the first electrode and the capacity insulating film and the oxide film may have electrical conductivity. Examples of oxide film of the metal element contained in the first electrode include ruthenium oxide (RuO) film and iridium oxide (IrO) film.
In the semiconductor device according to (1) or (2) above, the plug for connecting the first electrode and the semiconductor region may be made of metal or a metal compound and an anti-reaction film may be formed between the plug and the first electrode.
In the semiconductor device according to (1) or (2) above, the connecting portions for connecting the wires underlying the information storage capacity element and the main surface of the substrate may be made of metal or a metal compound and a metal silicide film may be formed on the main surface of the substrate carrying the connecting portions.
(3) A process of manufacturing a semiconductor device according to the present invention including: a substrate of a semiconductor or a substrate having a semiconductor layer as a surface thereof; a memory cell selection MISFET formed on a main surface of the substrate; and an information storage capacity element having a first electrode, a second electrode and a capacity insulating film, the first electrode being electrically connected to a semiconductor region functioning as source or drain of the memory cell selection MISFET, the second electrode being formed opposite to the first electrode, the capacity insulating film being put between the first and second electrodes, the process comprises: (a) a step of depositing an electrically conductive metal film of metal or an electrically conductive oxide or an electrically conductive nitride by one of a sputtering and a CVD method and forming the first electrode by processing the metal film or the oxide film or the nitride film; (b) a step of depositing an insulating metal oxide film on the first electrode by the CVD method; and (c) a step of forming the capacity insulating film by heat-treating the metal oxide film under 700xc2x0 C. to make grow a crystal of the metal oxide.
Examples of metal element contained in the film of metal or oxide or nitride thereof formed by deposition in step (a) above include ruthenium (Ru), tungsten (W), iridium (Ir) or platinum (Pt).
The rate of forming the film of metal or oxide or nitride thereof by deposition in step (a) above may be less than 200 nm/min.
The film of metal or oxide or nitride thereof formed by deposition in step (a) above may contain crystal oriented in a particular plane bearing. The plane bearing may be a (002).
(4) A process of manufacturing a semiconductor device accroding to the present invention including: a substrate of a semiconductor or a substrate having a semiconductor layer as a surface thereof; a memory cell selection MISFET formed on a main surface of the substrate; and an information storage capacity element having a first electrode, a second electrode and a capacity insulating film, the first electrode being electrically connected to a semiconductor region functioning as source or drain of the memory cell selection MISFET, the second electrode being formed opposite to the first electrode, the capacity insulating film being put between the first and second electrodes, the process comprises: (d) a step of forming the first electrode by one of a performance of deposition and process of an electrically conductive metal film and then oxidization of the metal film to produce ruggedness, and a performance of deposition of electrically conductive metal film, oxidization of the deposited metal film to produce ruggedness and then process of the metal film; (e) a step of depositing an insulating metal oxide film on the first electrode by the CVD method; and (f) a step of forming the capacity insulating film by heat-treating the metal oxide film under 700xc2x0 C. to grow a crystal of the metal oxide.
Examples of metal film that can be deposited in step (d) include a ruthenium (Ru) film, a tungsten (W) film, an iridium (Ir) film or a platinum (Pt) film.
The step (d) of producing ruggedness by oxidation may be a step of heat treatment conducted at temperature of lower than 700xc2x0 C. in an oxidizing atmosphere or that of plasma processing conducted at temperature of lower than 500xc2x0 C. in an oxidizing atmosphere and the gas of the oxidizing atmosphere may be oxygen (O2) gas, dinitrogen oxide (N2O) gas or nitrogen monoxide (NO) gas.
The first electrode may be formed by oxidizing part of the metal film and removing part or all of the unchanged (oxidized) region of the metal film by the etching method utilizing the difference of etching rate between the oxidized region and the unchanged region.
Prior to step (e), a film of metal same as the one contained in the first electrode may be formed selectively on the surface of the first electrode by the CVD method and the metal film may contain crystal oriented in a particular plane bearing. The plane bearing may be a (002).
In the manufacturing method according to (3) or (4) above, the metal oxide film deposited in step (b) or step (e), may be a tantalum oxide film. The tantalum oxide film may be formed by the deposition method using pentaetoxytantalum gas as source gas and the CVD method conducted in a temperature range between 450 and 500xc2x0 C. The tantalum oxide film may be an amorphous tantalum oxide film containing crystal of tantalum oxide therein.
In the manufacturing method according to (3) or (4) above, the heat treatment in one of the step (c) and the step (f) is conducted in one of: the first condition that temperature in an oxygen (O2) atmosphere is lower than 700xc2x0 C.; the second condition that temperature in an ozone (O3) atmosphere is lower than 600xc2x0 C.; the third condition that temperature in an dinitrogen oxide (N2O) gas atmosphere is between 600 and 650xc2x0 C.; the fourth condition that the second treatment that temperature in an atmosphere containing at least ozone is less than 600xc2x0 C. is conducted, after the first temperature that temperature in an non-oxidizing atmosphere is less than 700xc2x0 C.; and the fifth condition that the first treatment is conducted after the second treatment.
As a result of the heat treatment, crystal of the tantalum oxide film can be made to grow along the plane bearing of the underlying crystal.
The manufacturing method according to (3) or (4) above may further comprise a step of forming a connecting portion for connecting the distributing wires formed on the insulating film covering the memory cell selection MISFET, to the main surface of the substrate prior to the step (a) or the step (d) wherein a plurality of metal films constituting the connecting portion are piled up, and a metal silicide film is formed on the main surface of the substrate in the connecting portion after the heat treatment between silicon constituting the substrate and the metal element constituting the metal film contacting to the substrate in the piled metal film.
Furthermore, the present invention will be reiterated below.
1. A semiconductor device comprises: a semiconductor substrate having a main surface; a first MISFET having a gate electrode formed on the main surface of the semiconductor substrate and source and drain regions formed at both ends of the gate electrode; a first insulating film formed on the first MISFET; a second insulating film formed on the first insulating film and having a through hole for exposing a surface of the first insulating film; and a capacity element having a first electrode formed on both an inner wall of the through hole and a surface of the first insulating film present in the through hole and electrically connected to the source region or the drain region of the first MISFET, a dielectric film formed on the surface of the first electrode, and a second electrode formed on a surface of the dielectric film wherein the first electrode is made of a metal film oriented in a (002) plane.
2. The semiconductor device according to item 1, wherein the first electrode is made of ruthenium.
3. The semiconductor device according to item 2, wherein the dielectric film is made of a tantalum oxide film oriented in a (002) plane.
4. The semiconductor device according to item 3 further comprises: a second MISFET having a gate electrode formed on the main surface of the semiconductor substrate and a source region and a drain region formed at both ends of the gate electrode; and a silicide layer of a metal film with high melting point, the silicide film being formed on each surface of the source and drain regions wherein the silicide layer being formed under the first insulating film.
5. A process of manufacturing a semiconductor device comprises:
(a) a step of forming a first insulating film on a main surface of a semiconductor substrate; (b) a step of forming a second insulating film greater than the first insulating film in film thickness on the first insulating film; (c) a step of forming a through hole in the second insulating film for exposing a surface of the first insulating film; (d) a step of forming a ruthenium film oriented in a (002) plane on an inner wall of the through hole and the surface of the first insulating film in the through hole; (e) a step of depositing a tantalum oxide film on the ruthenium film; (f) a step of thermally treating the tantalum oxide film; and (g) a step of forming a metal film on the tantalum oxide film.
6. The process of manufacturing a semiconductor device according to item 5, wherein temperature of the heat treatment is lower than 700xc2x0 C.
7. A process of manufacturing a semiconductor device comprises:
(a) a step of forming first and second MISFETs having a gate electrode, a source region and a drain region on the main surface of a semiconductor substrate; (b) a step of forming a silicide layer having a metal with high melting point on respective surfaces of the source and drain regions; (c) a step forming a first insulating film on the first and second MISFETs; (d) a step of forming a second insulating film greater than the first insulating film in film thickness on the first insulating film; (e) a step of forming a through hole in the second insulating film, the through hole locating on the first MISFET and exposing the surface of the first insulating film; (f) a step of forming a first metal film oriented in a (002) plane on the inner wall of the through hole and on the surface of the first insulating film in the through hole; (g) a step of depositing a dielectric film on the first metal film; (h) a step of thermally treating the dielectric film; and (i) a step of forming a second metal film on the dielectric film.
8. The process of manufacturing a semiconductor device according to item 7, wherein the first metal film is made of ruthenium.
9. The process of manufacturing a semiconductor device according to item 8, wherein the dielectric film is made of tantalum oxide film oriented in a (002) plane.
10. The process of manufacturing a semiconductor device according to item 9, wherein the second electrode is made of ruthenium.
11. The process of manufacturing a semiconductor device according to item 8, wherein temperature of the heat treatment is lower than 700xc2x0 C.
12. A process of manufacturing a semiconductor device comprises: (a) a step of forming first and second MISFETs having a gate electrode, a source region and a drain region on a main surface of a semiconductor substrate; (b) a step of forming a silicide layer film having a metal with high melting point on both surfaces of the source and drain regions; (c) a step forming a first insulating film on the first and second MISFETs; (d) a step of forming a first metal film oriented in a (002) plane on the first insulating film; (e) a step of depositing a dielectric film on the first metal film; (f) a step of thermally treating the dielectric film; and (g) a step of forming a second metal film on the dielectric film.
13. The process of manufacturing a semiconductor device according to item 12, wherein the first metal film is made of ruthenium.
14. The process of manufacturing a semiconductor device according to item 12 wherein the second electrode is made of ruthenium.
15. The process of manufacturing a semiconductor device according to item 13, wherein the dielectric film is made of a tantalum oxide film oriented in a (002) plane.
The major effects of the present invention as disclosed in the patent application include the following.
(1) A capacity insulating film having a high thermal resistance and a high reliability and being capable of increasing the accumulated electric charge be provided.
(2) The tantalum oxide film can be crystallized by low temperature heat treatment without degrading the metal silicide film of the connecting portions in the distributing wires.
(3) The possible oxidation of the underlying substrate can be suppressed when crystallizing the tantalum oxide film.
(4) Any increase in the connection resistance of the connecting portions in the peripheral circuit region can be suppressed to provide a DRAM having a capacity insulating film showing a high dielectric constant and be adapted to achieve a higher degree of integration with an improved level of performance and reliability.
(5) The surface area of the lower electrode of the information storage capacity element can be increased to raise the accumulated electric charge.